FIG. 1 illustrates a top view of an exemplary conventional metal oxide semiconductor (MOS) cell 10 with gate, drain, source, and bulk (body) regions, each region including respective contacts. The width of the MOS channel (gate region) may be B and the length of the MOS channel may be G, whereas the lengths of the source and drain regions may be S and D, respectively. The length of the MOS cell 10 may be A, which may include the lengths of the source, gate and drain regions. In various embodiments, the dimensions B, S, G and D may be based on design rules of a particular process technology to achieve certain reliability and voltage capabilities, as is well known in the art. The total area of the MOS may be A×B.
The on-resistance (Ron) of the MOS cell 10 may depend at least in part on the dimensions of various regions. For example, a larger width B may result in a smaller Ron, and a smaller length G may result in a smaller Ron. By reducing the Ron, the number of times the MOS switches within a given time period may be increased, and thus, higher switching speeds and lower energy use per switching event may be attained.
However, in order to reduce the Ron, if the width B of the MOS channel is increased, the area of the MOS cell will also increase proportionally. An increased MOS area may result in chips with less computing power in the same area, or larger chips with increased manufacturing costs. Therefore, it may be desired to reduce the Ron without substantially increasing the area of the MOS.
One way to reduce the Ron consists of mirroring two basic MOS cells such that the drain regions of each cell overlap, as illustrated in the exemplary MOS array 20 of two MOS cells in FIG. 2. In the MOS array 20, the effective width B is doubled (as there are two MOS channels, each with a width of B), thereby decreasing the Ron, while the total area of the array 20 is less than double of the area of a single MOS cell (i.e., less than double of A×B). This structure may be repeated, as illustrated in the MOS cell array of FIG. 3, to obtain an even smaller Ron, with mirroring of a large number of basic MOS cells.
However, it may be desirable to further increase the channel width to decrease the Ron, without substantially increasing the area of the MOS cell.